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LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT * PERFORMANCE (1850 MHz) 29 dBm Output Power (P1dB) 16.5 dB Small-Signal Gain (SSG) 1.0 dB Noise Figure 42 dBm Output IP3 50% Power-Added Efficiency Evaluation Boards Available Featuring Lead Free Finish Package
FPD2250DFN
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DESCRIPTION AND APPLICATIONS The FPD2250DFN is a packaged depletion mode AlGaAs/InGaAs pseudomorphic High Electron Mobility Transistor (pHEMT). It utilizes a 0.25 m x 1500 m Schottky barrier Gate, defined by high-resolution stepper-based photolithography. The recessed and offset Gate structure minimizes parasitics to optimize performance, with an epitaxial structure designed for improved linearity over a range of bias conditions and input power levels. The FPD2250DFN is available in die form and in other packages. Typical applications include drivers or output stages in PCS/Cellular base station high-interceptpoint LNAs, WLL and WLAN systems, and other types of wireless infrastructure systems.
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ELECTRICAL SPECIFICATIONS AT 22C
Parameter Power at 1dB Gain Compression Small-Signal Gain Power-Added Efficiency Noise Figure Output Third-Order Intercept Point (from 15 to 5 dB below P1dB) Symbol P1dB SSG PAE NF IP3 Test Conditions VDS = 5 V; IDS = 50% IDSS VDS = 5 V; IDS = 50% IDSS VDS = 5 V; IDS = 50% IDSS; POUT = P1dB VDS = 5 V; IDS = 50% IDSS VDS = 5 V; IDS = 25% IDSS VDS = 5V; IDS = 50% IDSS Matched for optimal power Matched for best IP3 Saturated Drain-Source Current Maximum Drain-Source Current Transconductance Gate-Source Leakage Current Pinch-Off Voltage Gate-Source Breakdown Voltage Gate-Drain Breakdown Voltage IDSS IMAX GM IGSO |VP| |VBDGS| |VBDGD| VDS = 1.3 V; VGS = 0 V VDS = 1.3 V; VGS +1 V VDS = 1.3 V; VGS = 0 V VGS = -5 V VDS = 1.3 V; IDS = 2.25 mA IGS = 2.25 mA IGD = 2.25 mA 0.7 12 12 560 42 43 700 1.1 600 1 1.0 16 16 10 1.3 825 mA A mS A V V V dBm Min 28 15 Typ 29 16.5 50 1.0 0.8 1.75 Max Units dBm dB % dB RF SPECIFICATIONS MEASURED AT f = 1850 MHz USING CW SIGNAL
Phone: +1 408 850-5790 Fax: +1 408 850-5766
http://www.filtronic.co.uk/semis.com
Revised: 11/14/05 Email: sales@filcsi.com
LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT * ABSOLUTE MAXIMUM RATINGS1
Parameter Drain-Source Voltage Gate-Source Voltage Drain-Source Current Gate Current RF Input Power
2
FPD2250DFN
Symbol VDS VGS IDS IG PIN TCH TSTG PTOT Comp.
3
Test Conditions -3V < VGS < +0V 0V < VDS < +8V For VDS > 2V Forward or reverse current Under any acceptable bias state Under any acceptable bias state Non-Operating Storage See De-Rating Note below Under any bias conditions
Min
Max 8 -3 IDSS 22 525 175
Units V V mA mA mW C C W dB %
Channel Operating Temperature Storage Temperature Total Power Dissipation Gain Compression
1
-40
150 3.0 5
Simultaneous Combination of Limits 2 or more Max. Limits 80 2 TAmbient = 22C unless otherwise noted Max. RF Input Limit must be further limited if input VSWR > 2.5:1 3 Users should avoid exceeding 80% of 2 or more Limits simultaneously
Notes: * Operating conditions that exceed the Absolute Maximum Ratings will result in permanent damage to the device. * Total Power Dissipation defined as: PTOT (PDC + PIN) - POUT, where: PDC: DC Bias Power PIN: RF Input Power POUT: RF Output Power * Total Power Dissipation to be de-rated as follows above 22C: PTOT= 3.0W - (0.025W/C) x TPACK where TPACK = package lead temperature above 22C (coefficient of de-rating formula is the Thermal Conductivity) Example: For a 65C package lead temperature: PTOT = 3.0W - (0.025 x (65 - 22)) = 1.93W * The use of a filled via-hole directly beneath the exposed heatsink tab on the bottom of the package is strongly recommended to provide for adequate thermal management. Ideally the bottom of the circuit board is affixed to a heatsink or thermal radiator.
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HANDLING PRECAUTIONS To avoid damage to the devices care should be exercised during handling. Proper Electrostatic Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and testing. These devices should be treated as Class 1A per ESD-STM5.1-1998, Human Body Model. Further information on ESD control measures can be found in MIL-STD-1686 and MIL-HDBK-263. APPLICATIONS NOTES & DESIGN DATA Applications Notes are available from your local Filtronic Sales Representative or directly from the factory. Complete design data, including S-parameters, noise data, and large-signal models are available on the Filtronic web site. Evaluation Boards available upon request.
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Phone: +1 408 850-5790 Fax: +1 408 850-5766
http://www.filtronic.co.uk/semis.com
Revised: 11/14/05 Email: sales@filcsi.com
LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT
FPD2250DFN
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BIASING GUIDELINES Active bias circuits provide good performance stabilization over variations of operating temperature, but require a larger number of components compared to self-bias or dual-biased. Such circuits should include provisions to ensure that Gate bias is applied before Drain bias, otherwise the pHEMT may be induced to self-oscillate. Contact your Sales Representative for additional information. Dual-bias circuits are relatively simple to implement, but will require a regulated negative voltage supply for depletion-mode devices such as the FPD2250DFN. For standard Class A operation, a 50% of IDSS bias point is recommended. A small amount of RF gain expansion prior to the onset of compression is normal for this operating point. Note that pHEMTs, since they are "quasi- E/D mode" devices, exhibit Class AB traits when operated at 50% of IDSS. To achieve a larger separation between P1dB and IP3, an operating point in the 25% to 33% of IDSS range is suggested. Such Class AB operation will not degrade the IP3 performance. PACKAGE OUTLINE (dimensions in mm)
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All information and specifications subject to change without notice.
Phone: +1 408 850-5790 Fax: +1 408 850-5766
http://www.filtronic.co.uk/semis.com
Revised: 11/14/05 Email: sales@filcsi.com
LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT * PCB FOOT PRINT
FPD2250DFN
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TYPICAL I-V CHARACTERISTICS
DC IV Curves FPD2250SOT89 0.90 0.80 0.70 Drain-Source Current (A) 0.60 0.50 0.40 0.30 0.20 0.10 0.00 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Drain-Source Voltage (V)
VG=-1.50V VG=-1.25V VG=-1.00V VG=-0.75V VG=-0.50V VG=-0.25V VG=0V
Phone: +1 408 850-5790 Fax: +1 408 850-5766
http://www.filtronic.co.uk/semis.com
Revised: 11/14/05 Email: sales@filcsi.com
LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT
FPD2250DFN
Note: The recommended method for measuring IDSS, or any particular IDS, is to set the Drain-Source voltage (VDS) at 1.3V. This measurement point avoids the onset of spurious self-oscillation which would normally distort the current measurement (this effect has been filtered from the I-V curves presented above). Setting the VDS > 1.3V will generally cause errors in the current measurements, even in stabilized circuits. Recommendation: Traditionally a device's IDSS rating (IDS at VGS = 0V) was used as a predictor of RF power, and for MESFETs there is a correlation between IDSS and P1dB (power at 1dB gain compression). For pHEMTs it can be shown that there is no meaningful statistical correlation between IDSS and P1dB; specifically a linear regression analysis shows r2 < 0.7, and the regression fails the F-statistic test. IDSS is sometimes useful as a guide to circuit tuning, since the S22 does vary with the quiescent operating point IDS.
Phone: +1 408 850-5790 Fax: +1 408 850-5766
http://www.filtronic.co.uk/semis.com
Revised: 11/14/05 Email: sales@filcsi.com

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